TRAINING

CERTFIEDIN ADVANCED DIPLOMAIN ASICDESIGN&VERIFICATION

contact:9640648777

ADVANCE DIGITAL ELECTRONICS

  • IntroductiontoVLSI
  • ASICDesignFlow
  • LogicGates
  • NumberSystemsandCodeConversions
  • K-maps
  • CombinationalLogicCircuits
  • SequentialLogicCircuits
  • Flip-Flops
  • Counters
  • Registers
  • FiniteStateMachine
  • MemoryOrganizations
  • ProgrammableLogicDevices(FPGA’s)



  • LINUX

  • IntroductiontoLinuxOS
  • BasicsofLinuxcommands
  • BasicsofShellscripting
  • BasicsofPerlscripting

  • VERILOG HDL

  • IntroductiontoVerilogHDL
  • ModelingConcepts
  • GateLevelModeling
  • DataFlowModeling
  • BehaviouralModeling
  • StructuralModeling
  • SwitchLevelModeling
  •     DataTypes
        Operators
        ProcedureandFlowOfControlStatement
  • DesigningofCombinationalCircuits
  • DesigningofSequentialCircuits
  • FSMDesignModeling
  • DesigningofMemories
  • WritingTestbenchusingVerilog
  • TaskandFunctions
  • SystemTasks
  • CompilerDirectives
  • AdvanceNetsinVerilog
  • BusFunctionalModeling
  • VerilogBasedAssertions
  • CodeCoverage&FPGAImplementation

  • SYSTEM VERILOG& UVM

  • IntroductiontoVeriöcationPlan
  • IntroductiontoSystemVerilog
  • Datatypes
  • Procedural&FlowControlStatements
  • Arrays
  • TaskAndFunctions
  • InterfacesandClockingBlock
  • ProgramBlocks
  • Fork–JoinStatements
  • OOPSConcepts
  • RandomizationandConstraints
  • Mailboxes
  • Semaphores
  • Events
  • VirtualInterfaces
  • Assertions
  • FunctionalCoverage
  • Packages
  • WritingTestbenchinSystemVerilog
  • ProjectsupportedbasedonMethodology
  • EDATOOLS
  • QuestaSim
  • Modelsim
  • XilinxISE

  • PHYSICAL DESIGN

  • TrendsAndChallengesInVLSI
  • ASICFlow
  • IntroductionofTransistors
  • IntroductionofCMOSTechnology
  • StickDiagrams
  • Lambda–Rules
  • Layouts
  • ARCHITECTURE

  • SOCBusStructure
  • SOCProcessorArchitecture
  • SOCperipherals

  • STA(STATICTIMINGANALYSIS)

  • FundamentalsofDelaycalculations
  • (wiremodeling).
  • Setup/HoldTimedefinitions&
  • SlackCalculations.
  • DifferentTimingPathAnalysis.
  • Analysis&approachtominimizethetiming
  • violations.
  • STAConstraintdevelopment.
  • LOGICDESIGN

  • FSMDesign&FIFODesign
  • HandshakingProtocol’s
  • MathFunctionImplementation
  • ResetDesign
  • ClockManagement

  • PLACE&ROUTE

  • FloorPlanning
  • I/ORing&PowerGridPlanning
  • PlacementMethodologies
  • CTS(ClockTreeSynthesis)
  • Routing&TimingOptimization
  • EDATOOLS

    MicroWind–Layout

    DSCH–Schematics

    H-Spice&SpiceLanguage(optional


    DFT(DESIGNFORTESTABILITY)

  • FaultModels
  • ATPGAlgorithms
  • At-SpeedTesting
  • IDDQTesting&MemoryBIST
  • I/OTesting
  • PatternGeneration